Ad converter and solid-state imaging apparatus using the same

ABSTRACT

There is a need to provide an AD converter capable of reducing occurrence of a noise. An AD converter includes an operational amplifier and a clip circuit. The operational amplifier receives ramp voltage and voltage for an analog signal and allows output terminal voltage to transition from an H level to an L level when a change in the ramp voltage reaches the voltage for the analog signal. The clip circuit fixes an output terminal of the operational amplifier to clipping voltage after output voltage for the operational amplifier reaches threshold voltage for a latch circuit. Therefore, the AD converter can limit a range of output voltage, as a source of noise, for the operational amplifier and eliminate an unnecessary change in the output voltage after the threshold voltage for the latch circuit is reached.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation of U.S. application Ser. No.13/707,198, filed Dec. 6, 2012, which claims benefit of priority fromthe prior Japanese Application No. 2011-269034, filed on Nov. 8, 2011;the entire contents of all of which are incorporated herein byreference.

BACKGROUND

The present invention relates to an AD converter and a solid-stateimaging apparatus using the same. More particularly, the inventionrelates to an AD converter to convert an analog signal into a digitalsignal and a solid-state imaging apparatus using the AD converter.

A solid-state imaging apparatus such as a CMOS (Complementary MetalOxide Semiconductor) sensor includes more than one pixel circuitarranged at more than one row and column. Each pixel circuitcorresponding to the selected row outputs an analog signal at a levelcorresponding to the amount of incident light. The columns are providedwith more than one AD (Analog to Digital) converter. Each AD converterconverts an analog signal output from the pixel circuit at thecorresponding column into a digital signal.

Such a solid-state imaging apparatus includes an increasing number of ADconverters as the number of pixels increases. To shorten the processingtime, more than one AD converter simultaneously performs AD conversionon output signals from pixel circuits corresponding to the selected row.The AD converters are provided with a bias voltage supply line in commonto decrease consumption current or reduce a chip area. The AD converterconfiguration is simplified.

The solid-state imaging apparatus disclosed in patent document 1suppresses a power supply noise when more than one comparison circuitoperates. For this purpose, the solid-state imaging apparatus usesdifferent bias current values for the comparison circuits and therebyapplies different operation timings to the comparison circuits.

The solid-state imaging apparatus disclosed in patent document 2suppresses an effect of power supply noise on a comparison circuit. Forthis purpose, a capacitor is coupled between a power supply line and asignal line to feed a potential variation on the power supply line backto the signal line.

Patent Document 1: Japanese Unexamined Patent Publication No.2009-118035

Patent Document 2: Japanese Unexamined Patent Publication No.2007-281540

SUMMARY

A solid-state imaging apparatus of the related art drastically changesan output signal from the comparison circuit in the AD converter whenthe output signal inverts. This varies a voltage on the bias voltagesupply line due to parasitic capacitance and causes or propagates anoise.

The technology described in patent document 1 uses different operationtimings for the comparison circuits and therefore decreases an overalloperation speed. The technology described in patent document 2 providesa capacitor for each comparison circuit and therefore increases thecircuit area.

It is, therefore, an object of the invention to provide an AD convertercapable of reducing noise occurrence and a solid-state imaging apparatususing the AD converter.

An AD converter according to an embodiment includes a clip circuit thatfixes voltage at an output node of a comparison circuit to a clippingvoltage after the voltage at the output node of the comparison circuitreaches a specified voltage.

The AD converter according to the embodiment fixes voltage at the outputnode of the comparison circuit to a clipping voltage after the voltageat the output node of the comparison circuit reaches a specifiedvoltage. Therefore, the AD converter can eliminate an output voltagerange as a noise source that drastically changes after a specifiedvoltage is reached. The AD converter can reduce occurrence of a noise.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram illustrating a configuration of a solid-stateimaging apparatus according to a first embodiment of the invention;

FIG. 2 is a block diagram illustrating a configuration of a controlcircuit illustrated in FIG. 1;

FIG. 3 is a block diagram illustrating a configuration of an ADconverter illustrated in FIG. 2;

FIG. 4 is a circuit diagram illustrating a configuration of anoperational amplifier illustrated in FIG. 3;

FIGS. 5A through 5F are timing charts illustrating operations of the ADconverter illustrated in FIG. 3;

FIG. 6 is a circuit block diagram illustrating a comparative example ofthe first embodiment:

FIGS. 7A through 7F are timing charts illustrating an effect of thefirst embodiment:

FIG. 8 is a circuit block diagram illustrating a first modification ofthe first embodiment;

FIG. 9 is a circuit block diagram illustrating a second modification ofthe first embodiment;

FIG. 10 is a circuit block diagram illustrating a third modification ofthe first embodiment;

FIG. 11 is a circuit block diagram illustrating a fourth modification ofthe first embodiment;

FIG. 12 is a circuit block diagram illustrating a fifth modification ofthe first embodiment;

FIG. 13 is a circuit block diagram illustrating a sixth modification ofthe first embodiment;

FIG. 14 is a circuit block diagram illustrating a seventh modificationof the first embodiment;

FIG. 15 is a circuit block diagram illustrating an eighth modificationof the first embodiment;

FIG. 16 is a circuit block diagram illustrating a ninth modification ofthe first embodiment;

FIG. 17 is a circuit block diagram illustrating a tenth modification ofthe first embodiment;

FIG. 18 is a block diagram illustrating a configuration of a solid-stateimaging apparatus according to a second embodiment of the invention;

FIG. 19 is a block diagram illustrating a configuration of an ADconverter illustrated in FIG. 18;

FIG. 20 is a circuit block diagram illustrating a series of ADconverters illustrated in FIG. 18;

FIG. 21 is a timing chart illustrating relationship between an outputvoltage and a clipping voltage for the AD converter illustrated in FIG.19; and

FIG. 22 is a timing chart illustrating operations of the AD converterillustrated in FIG. 19.

DETAILED DESCRIPTION First Embodiment

As illustrated in FIG. 1, a solid-state imaging apparatus according tothe first embodiment of the invention includes a pixel array 1, avertical scanning circuit 5, a control circuit 6, a horizontal scanningcircuit 7, and more than one AD converter (AD) 8. The pixel array 1includes more than one pixel circuit 2 provided for rows and columns,more than one row selection line group 3 provided for rows, and morethan one signal line 4 provided for columns.

The vertical scanning circuit 5 sequentially selects rows at a specifiedtime interval. The vertical scanning circuit 5 activates each pixelcircuit 2 through the row selection line group 3 corresponding to theselected row. The pixel circuit 2 for the selected row outputs an analogsignal for reference voltage VIB to the corresponding signal line 4during a first period and outputs an analog signal for signal voltageVIP to the corresponding signal line 4 during a second period. The pixelcircuit 2 outputs the reference voltage VIB if no incident light entersthe pixel circuit 2. The pixel circuit 2 outputs the signal voltage VIPif the light enters the pixel circuit 2. A difference between the signalvoltage VIP and the reference voltage VIB is equivalent to a voltage atthe level corresponding to the amount of incident light entering thepixel circuit 2.

The control circuit 6 controls an entire solid-state image sensor. Thehorizontal scanning circuit 7 sequentially selects output values fromthe AD converters 8 corresponding to the signal lines 4 at a specifiedtime interval while the vertical scanning circuit 5 selects one row. TheAD converters 8 are coupled to the signal lines 4.

Each AD converter 8 is supplied with an analog signal from the activatedpixel circuit 2 via the signal line 4. The AD converter 8 converts theanalog signal into a digital signal DO based on ramp voltage VR from thecontrol circuit 6, for example. The AD converter 8 outputs the generateddigital signal DO to the outside via a data bus when the horizontalscanning circuit 7 selects the corresponding signal line 4.

As illustrated in FIG. 2, the control circuit 6 includes a ramp voltagegenerator circuit 10, a counter 11, a bias generator circuit 12, and asignal generator circuit 13. The ramp voltage generator circuit 10generates ramp voltage VR and supplies it to AD converters 8 each timethe vertical scanning circuit 5 selects one row. The ramp voltage VRdecreases in proportion to the time from a given measurement start time.For example, the ramp voltage generator circuit 10 includes a counterand a DA converter. The counter counts the number of pulses in a clocksignal in response to a start signal. The DA converter converts a countvalue (digital signal) from the counter into the ramp voltage VR. Inthis example, the ramp voltage VR is assumed to gradually decrease fromthe highest value.

The counter 11 counts the number of pulses in the clock signal from theabove-mentioned measurement start time and supplies the AD converters 8with a digital signal CT indicating the count value. The bias generatorcircuit 12 generates less temperature-dependent bias voltages VP and VN.The AD converters 8 are provided with bias voltage supply lines VPL andVNL in common. The bias voltage VP generated from the bias generatorcircuit 12 is supplied to the AD converters 8 via the bias voltagesupply line VPL. The bias voltage VN generated from the bias generatorcircuit 12 is supplied to the AD converters 8 via the bias voltagesupply line VNL. The signal generator circuit 13 generates controlsignals containing a reset signal RST and supplies the generated signalsto the AD converters 8.

The AD converter 8 is supplied with an analog signal via thecorresponding signal line 4 and converts the analog signal into thedigital signal DO based on the ramp voltage VR, the digital signal CT,the bias voltages VP and VN, and the control signal RST.

As illustrated in FIG. 3, the AD converter 8 includes an input terminalTI, switches SW1 and SW2, capacitors C1 and C2, an operational amplifier20, a latch circuit 21, and a clip circuit 27. The input terminal TIreceives voltage VI for an analog signal. One terminal of the switch SW1is coupled to the input terminal TI and the other terminal thereof iscoupled to a non-inverting input terminal (positive terminal) of theoperational amplifier 20. The switch SW2 is coupled between an outputterminal and an inverting input terminal (negative terminal) of theoperational amplifier 20. A control signal from the signal generatorcircuit 13 in the control circuit 6 controls the switches SW1 and SW2.

The capacitor C1 is coupled between the inverting input terminal of theoperational amplifier 20 and a line for fixed potential (e.g., groundvoltage VSS). One electrode of the capacitor C2 receives the rampvoltage VR and the other electrode thereof is coupled to thenon-inverting input terminal (positive terminal) of the operationalamplifier 20.

During the first period, the reference voltage VIB (black level) of ananalog signal is supplied to the input terminal TI. The switches SW1 andSW2 turn on. The capacitor C1 is charged with the reference voltage VIBof the analog signal. During the second period, the signal voltage VIPof the analog signal is supplied to the input terminal TI. The switchSW1 turns on and the switch SW2 turns off. The capacitor C2 is chargedwith the signal voltage VIP of the analog signal. The voltage at thenon-inverting input terminal gradually decreases if the switches SW1 andSW2 turn off and the ramp voltage VR gradually decreases. An outputvoltage from the operational amplifier 20 is inverted to the L levelfrom the H level if the voltage of the non-inverting input terminaldrops lower than the voltage at the inverting input terminal.

As illustrated in FIG. 4, the operational amplifier 20 includes anon-inverting input terminal T1, an inverting input terminal T2, anoutput terminal T3, P-channel MOS transistors 31 through 34, N-channelMOS transistors 35 through 38, and a constant current source 39. Gatesof the transistors 37 and 38 are coupled to the input terminals T1 andT2, respectively. The sources thereof are coupled to a node N39. Thetransistors 37 and 38 configure a differential transistor pair. Theconstant current source 39 allows the node N39 to apply a constantcurrent to the line for the ground voltage VSS.

The transistors 31, 33, and 35 are parallel coupled between a line for apower supply voltage VDD and a drain of the transistor 37. Thetransistors 32, 34, and 36 are parallel coupled between the line for apower supply voltage VDD and a drain of the transistor 38. The outputterminal T3 is coupled drains of the transistors 34 and 36.

Gates of the transistors 31 and 32 are coupled to a drain of thetransistor 33. The transistors 31 and 32 configure a current mirrorcircuit. A current of the same value is applied to the transistors 31and 32.

Gates of the transistors 33 and 34 receive bias voltage VP. A voltage atthe drain of the transistor 31 equals the sum of the bias voltage VP andan absolute value of the threshold voltage for the transistor 33. Avoltage at the drain of the transistor 32 equals the sum of the biasvoltage VP and an absolute value of the threshold voltage for thetransistor 34. The same voltage is applied to the trains of thetransistors 31 and 32 because the transistors 33 and 34 use the samethreshold voltage. Therefore, the current mirror circuit of thetransistors 31 and 32 maintains high precision.

Gates of the transistors 35 and 36 receive the bias voltage VN. Avoltage at the drain of the transistor 37 is obtained by subtracting thethreshold voltage for the transistor 35 from the bias voltage VN. Avoltage at the drain of the transistor 38 is obtained by subtracting thethreshold voltage for the transistor 36 from the bias voltage VN. Thesame voltage is applied to the trains of the transistors 37 and 38because the transistors 35 and 36 use the same threshold voltage.Therefore, the differential transistor pair of the transistors 37 and 38maintains high precision.

A current flowing through the transistors 31 through 35 and 37 is largerthan a current flowing through the transistors 36 and 38 if the voltageat the non-inverting input terminal T1 is higher than the voltage at theinverting input terminal T2. The output terminal T3 is set to the Hlevel. A current flowing through the transistors 31 through 35 and 37 issmaller than a current flowing through the transistors 36 and 38 if thevoltage at the non-inverting input terminal T1 is lower than the voltageat the inverting input terminal T2. The output terminal T3 is set to theL level.

Parasitic capacitance C3 exists between the output terminal T3 and theline between the gates of the transistors 33 and 34. Parasiticcapacitance C4 exists between the output terminal T3 and the linebetween the gates of the transistors 35 and 36. Transient currents I3and I4 are applied to the bias voltage supply lines VPL and VNL via theparasitic capacitances C3 and C4 when the voltage at the output terminalT3 changes to the H level from the L level, or vice versa.

The transient currents I3 and I4 cause voltage distribution on the biasvoltage supply lines VPL and VNL. The operational amplifiers 20 aresupplied with the bias voltages VP and VN having different values. Thebias voltages VP and VN having different values cause different responsespeeds to the operational amplifier 20. The AD converters 8 output thedigital signals DO having different values even if analog signals at thesame level are output to the signal lines 4. As a result, a noise occurson an image. The first embodiment decreases a noise level.

Now referring back to FIG. 3, the latch circuit 21 includes a P-channelMOS transistor 22, an N-channel MOS transistor 23, inverters 24 and 25,and a counter latch 26. The source of a transistor 22 receives the powersupply voltage VDD. The gate thereof receives an output signal from theoperational amplifier 20. The drain thereof is coupled to a node N22.The drain of a transistor 23 is coupled to the node N22. The gatethereof receives the reset signal RST. The source thereof receives theground voltage VSS.

The transistor 23 turns on to reset the node N22 to the L level (groundvoltage VSS) if the reset signal RST is set to the H level as an activelevel for a specified time. An output voltage from the operationalamplifier 20 transitions to the ground voltage VSS from the power supplyvoltage VDD. The transistor 22 turns on to raise the node N22 to the Hlevel from the L level if a difference between the power supply voltageVDD and the output voltage from the operational amplifier 20 exceeds anabsolute value of the threshold voltage for the transistor 22.

The inverter 24 outputs an inversion signal ST for a signal occurring atthe node N22 to the node N25. The inverter 25 outputs an inversionsignal for the signal ST occurring at the node N25 to the node N22. Theinverters 24 and 25 configure a latch circuit.

The counter latch 26 latches the digital signal CT from the counter 11when the stop signal ST occurring at the node N25 lowers to the L levelfrom the H level. The counter latch 26 outputs the latched digitalsignal CT as the digital signal DO that notifies the amount of incidentlight to the pixel circuit 2 when the horizontal scanning circuit 7selects the corresponding signal line 4.

The clip circuit 27 includes P-channel MOS transistors 28 and 29 and anN-channel MOS transistor 30 that are coupled in series between a linefor the power supply voltage VDD and an output terminal of theoperational amplifier 20. The gate of the transistor 28 receives acontrol signal ONT. The gate of the transistor 29 receives the stopsignal ST. The gate of the transistor 30 is coupled to the line for thepower supply voltage VDD.

The control signal CNT is set to the H level to turn off the transistor28 while the switch SW2 turns on. The control signal CNT is set to the Llevel to turn on the transistor 28 while the switch SW2 turns off. Thetransistor 29 turns on and the transistor 30 operates as a diode whenthe stop signal ST is inverted to the L level from the H level. Currentdrive capabilities for the transistors 28 through 30 are set to valueslarger than a value corresponding to the capability for the operationalamplifier 20. When the transistors 28 and 29 turn on, the voltage at theoutput terminal of the operational amplifier 20 is fixed to a clippingvoltage VC equivalent to the power supply voltage VDD minus thethreshold voltage for the transistor 30.

FIGS. 5A through 5F are timing charts illustrating operations of the ADconverter 8 illustrated in FIGS. 3 and 4. If the vertical scanningcircuit 5 selects a row, the pixel circuits 2 corresponding to the roware activated. Each of the pixel circuits 2 is reset and outputsreference voltage VIB (black level) of the analog signal to the signalline 4 (time t0).

At time t1, only the switch SW1 turns on for a specified time to chargethe non-inverting input terminal T1 of the operational amplifier 20 withthe reference voltage VIB of the analog signal. At time t2, only theswitch SW2 turns on for a specified time to charge the inverting inputterminal T2 of the operational amplifier 20 with the reference voltageVIB of the analog signal.

The switches SW1 and SW2 turn off. Each pixel circuit 2 corresponding tothe selected row then outputs the signal voltage VIP of the analogsignal to the signal line 4. At time t3, only the switch SW1 turns onfor a specified time to charge the non-inverting input terminal T2 ofthe operational amplifier 20 with the signal voltage VIP of the analogsignal. The output terminal T3 of the operational amplifier 20 is set tothe H level (VH).

The switch SW1 turns off. At time t4, the ramp voltage VR is then raisedto a highest value VRH from a wait value VRO. The highest value VRH isobtained by adding a margin voltage to the wait value VRO. If the rampvoltage VR is raised to the highest value VRH from the wait value VRO,capacitive coupling via the capacitor C2 increases the voltage at thenon-inverting input terminal T1 by the margin voltage.

At time t5, the ramp voltage VR linearly drops from the highest valueVRH to a lowest value VRL in proportion to the time lapse. While theramp voltage VR drops in proportion to the time, the capacitive couplingvia the capacitor C2 drops the voltage at the non-inverting inputterminal T1 in proportion to the time. At time t6, the voltage at thenon-inverting input terminal T1 becomes lower than the voltage at theinverting input terminal T2. The operational amplifier 20 then allowsthe voltage at the output terminal T3 to transition to the L level VLfrom the H level VH.

The voltage at the output terminal T3 of the operational amplifier 20reaches a voltage equivalent to the power supply voltage VDD minus anabsolute value of the threshold voltage for the transistor 22 in FIG. 3.The transistor 22 then turns on to lower the stop signal ST to the Llevel from the H level. The output signal CT from the counter 11 isthereby latched to the counter latch 26. The latched signal CT isequivalent to the digital signal DO. Time Tc from time t5 to time t6corresponds to a difference between the signal voltage VIP and thereference voltage VIB for the analog signal. Increasing the signalvoltage VIP elongates time Tc.

Lowering the stop signal ST to the L level turns on the transistor 29 ofthe clip circuit 27 in FIG. 3. The output terminal T3 of the operationalamplifier 20 is fixed to the clipping voltage VC. The clipping voltageVC is lower than the power supply voltage VDD by the threshold voltagefor the transistor 30 and is higher than the L level VL for the outputvoltage from the operational amplifier 20. If the transient currents I3and I4 occur on the bias voltage supply lines VPL and VNL, changing theoutput voltage from the operational amplifier 20 can keep the transientcurrents I3 and I4 at the low level and decrease a noise level.

Comparative Examples

The following describes effects of the first embodiment in detail. FIG.6 is a circuit block diagram illustrating a configuration of an ADconverter 40 as a comparative example of the first embodiment and iscompared to FIG. 3. The AD converter 40 in FIG. 6 differs from the ADconverter 8 in FIG. 3 in that the clip circuit 27 is eliminated. Becausethe AD converter 40 lacks the clip circuit 27, the output voltage fromthe operational amplifier 20 changes to the L level VL from the H levelVH. Therefore, a change in the output voltage from the operationalamplifier 20 allows large transient currents I3 and I4 to flow throughthe bias voltage supply lines VPL and VNL and causes a large noise.

FIGS. 7A and 7B are timing charts schematically illustrating changes inan output voltage VO1 and a transient current IT1 for the operationalamplifiers 20 in the AD converter 40 according to a comparative examplewhen the operational amplifier 20 is configured to fast respond. Asillustrated in FIG. 7A, the output voltage VO1 from the operationalamplifiers 20 drastically lowers from the H level VH to the L level VL.The output voltage VO1 from the operational amplifiers 20 lowers atdifferent times. As illustrated in FIG. 7B, the large transient currentIT1, like a pulse, flows through the operational amplifiers 20 inresponse to the falling edge of the output voltage VO1 from theoperational amplifiers 20. The transient current IT1 has a small effecton the other operational amplifiers 20 because the transient current IT1flows through each operational amplifier 20 in a short period of time.However, the fast responding operational amplifier 20 unfavorablyconsumes a large amount of current and occupies a large circuit area.

FIGS. 7C and 7D are timing charts schematically illustrating changes inan output voltage VO2 and a transient current IT2 for the operationalamplifiers 20 in the AD converter 40 according to a comparative examplewhen the operational amplifier 20 is configured to slow respond. Asillustrated in FIG. 7C, the output voltage VO2 from the operationalamplifiers 20 gradually transitions from the H level VH to the L levelVL. The transient current IT2 flows through each operational amplifier20 in a predetermined duration. The transient currents IT2 of theoperational amplifiers 20 overlap with each other. As illustrated inFIG. 7D, the transient current IT2 having a trapezoid waveform flowsthrough the bias voltage supply lines VPL, and VNL. This transientcurrent IT2 affects the performance of each operational amplifier 20such as a response speed and causes a noise. However, the slowresponding operational amplifier 20 favorably consumes a small amount ofcurrent and occupies a small circuit area.

FIGS. 7E and 7F are timing charts schematically illustrating changes inan output voltage VO3 and a transient current IT3 for the operationalamplifiers 20 in the AD converter 8 according to the first embodiment.The first embodiment reduces the consumption current and the circuitarea. Therefore, each operational amplifier 20 is configured to slowrespond. For this reason, the output voltage VO3 from the operationalamplifiers 20 gradually transitions from the H level VH to the L levelVL as illustrated in FIG. 7E. The output voltage VO3 from theoperational amplifier 20 is fixed to the clipping voltage VC lower thana threshold voltage VTH and does not become lower than the clippingvoltage VC. The threshold voltage VTH is obtained by subtracting anabsolute value of the threshold voltage for the transistor 22 from thepower supply voltage VDD. Accordingly, the output voltage VO3 from theoperational amplifier 20 is forced to small amplitude. As illustrated inFIG. 7F, the transient current IT3 also decreases. Therefore, thetransient current IT3 less affects the performance of each operationalamplifier 20 such as the response speed than the comparative example.The noise level is forced to be small.

The first embodiment has described the case where an output signal fromthe operational amplifier transitions from the H level to the L level. Asimilar configuration is obviously applicable to a case where an outputsignal from the operational amplifier transitions from the L level tothe H level.

The first embodiment fixes a voltage at the output terminal T3 of theoperational amplifier 20 to the clipping voltage VC lower than thethreshold voltage VTH for the latch circuit 21 while the thresholdvoltage VTH is obtained by subtracting an absolute value of thethreshold voltage for the transistor 22 from the power supply voltageVDD. The invention is not limited thereto. The clipping voltage VC maybe higher than the threshold voltage VTH for the latch circuit 21. Inthis case, a transient current IT4 may flow through the bias voltagesupply lines VPL and VNL if the clipping voltage VC is applied to theoutput terminal T3 of the operational amplifier 20. The transientcurrent IT4 has the polarity opposite the transient current IT3illustrated in FIG. 7F. The transient current IT4 may cancel thetransient current IT3.

If the AD converter 8 is used for the other purposes, the control signalCNT may be fixed to the H level. The transistor 28 may turn off. Theclip circuit 27 may be fixed to be inactive.

First Modification

The following describes various modifications of the first embodiment.The modifications replace the AD converters 8 with the other ADconverters. FIG. 8 illustrates an AD converter 41 according to the firstmodification. A clip circuit 42 and a latch circuit 43 replace the clipcircuit 27 and the latch circuit 21, respectively. The clip circuit 42is provided by removing the transistor 28 from the clip circuit 27. Thelatch circuit 43 is provided by adding a P-channel MOS transistor 44 tothe latch circuit 21. The control signal CNT is removed. A reset signalRSTA replaces the reset signal RST. The transistors 29 and 30 of theclip circuit 42 are coupled in series between the line for the powersupply voltage VDD and the output terminal of the operational amplifier20. The source of the transistor 44 is coupled to the drain of thetransistor 22. The drain thereof is coupled to the node N22. The gatesof the transistors 23 and 44 receive the reset signal RSTA.

The reset signal RSTA is set to the H level while the switch SW2 turnson. The transistor 44 thereby turns off to turn on the transistor 23.The node N22 is set to the L level to turn off the transistor 29 andstop supplying the clipping voltage VC. The first modification canprovide the same effect as the first embodiment, eliminate the signalline for supplying the control signal CNT, and simplify theconfiguration.

Second Modification

FIG. 9 illustrates an AD converter 45 according to the secondmodification. A clip circuit 46 replaces the clip circuit 27. AnN-channel MOS transistor 47 configures the switch SW2. The clip circuit46 is provided by removing the transistor 29 from the clip circuit 27.The transistors 28 and 30 of the clip circuit 42 are coupled in seriesbetween the line for the power supply voltage VDD and the outputterminal of the operational amplifier 20. The drain of the transistor 47is coupled to the output terminal of the operational amplifier 20. Thegate thereof receives the control signal CNT. The source thereof iscoupled to the inverting input terminal of the operational amplifier 20.

The control signal CNT is set to the H level while the switch SW2(transistor 47) turns on. The transistor 28 thereby turns off to stopsupplying the clipping voltage VC. The control signal CNT is set to theL level while the switch SW2 (transistor 47) turns off. The transistor28 thereby turns on to supply the clipping voltage VC to the outputterminal of the operational amplifier 20.

The second modification can provide the same effect as the firstembodiment and use one signal line to control the transistor 28 and theswitch SW2 (transistor 47). The transistor 29 is eliminated to simplifythe configuration. However, the second modification limits the clippingvoltage VC to being lower than the threshold voltage VTH for the latchcircuit 21.

Third Embodiment

FIG. 10 illustrates an AD converter 50 according to the thirdmodification. A clip circuit 51 replaces the clip circuit 27. The clipcircuit 51 is provided by removing the transistors 28 and 29 from theclip circuit 27. The source of the transistor 30 in the clip circuit 51is directly coupled to the line for the power supply voltage VDD. Thetransistor 30 configures a diode. The clipping voltage VC is alwayssupplied to the output terminal of the operational amplifier 20. Theclipping voltage VC is limited to being lower than the reference voltageVIB for an analog signal and being lower than the threshold voltage VTHfor the latch circuit 21. The third modification can provide the sameeffect as the first embodiment and simplify the configuration.

Fourth Modification

FIG. 11 illustrates an AD converter 55 according to the fourthmodification. A clip circuit 56 replaces the clip circuit 27. The clipcircuit 56 includes the transistor 30 whose gate receives controlvoltage VCA. The clipping voltage VC is obtained by subtracting thethreshold voltage for the transistor 30 from the control voltage VCA.Adjusting the control voltage VCA can set the clipping voltage VC to anintended value. The fourth modification can provide the same effect asthe first embodiment and set the clipping voltage VC to an intendedvalue.

Fifth Modification

FIG. 12 illustrates an AD converter 60 according to the fifthmodification. A clip circuit 61 and a latch circuit 62 replace the clipcircuit 27 and the latch circuit 21, respectively. The clip circuit 61is provided by removing the transistors 28 and 29 from the clip circuit27. The latch circuit 62 is provided by adding an inverter 63 to thelatch circuit 43 in FIG. 8. The control signal CNT is removed.

The reset signal RSTA replaces the reset signal RST. The transistor 30in the clip circuit 61 is coupled between the line for the power supplyvoltage VDD and the output terminal of the operational amplifier 20. Theinverter 63 inverts the stop signal ST appearing at the node N25. Aninversion signal /ST for the stop signal ST is supplied to the gate ofthe transistor 30.

The reset signal RSTA is set to the H level while the switch SW2 turnson. The transistor 44 thereby turns off to turn on the transistor 23.The node N22 is set to the L level to turn off the transistor 30 andstop supplying the clipping voltage VC.

A signal output from the operational amplifier 20 transitions from the Hlevel to the L level. The transistor then turns on to set the node N22to the H level and set the signal /ST to the H level (power supplyvoltage VDD). The transistor 30 thereby cooperates with the diode to fixa voltage at the output terminal of the operational amplifier 20 to theclipping voltage VC. The fifth modification can also provide the sameeffect as the first embodiment.

Sixth Modification

FIG. 13 illustrates an AD converter 65 according to the sixthmodification. A clip circuit 66 replaces the clip circuit 27. The clipcircuit 66 is provided by removing the transistor 30 from the clipcircuit 27. The source of the transistor 28 receives the clippingvoltage VC. The drain thereof is coupled to the output terminal of theoperational amplifier 20 via the transistor 29. The clipping voltage VCis adjustable to an intended value. The sixth modification can providethe same effect as the first embodiment and adjust the clipping voltageVC to an intended value.

Seventh Modification

FIG. 14 illustrates an AD converter 70 according to the seventhmodification. The source of the transistor 30 in the clip circuit 27 iscoupled to the non-inverting input terminal of the operational amplifier20. An output signal from the operational amplifier 20 transitions fromthe H level to the L level to turn on the transistor 22 in the latchcircuit 21. The stop signal ST then lowers to the L level from the Hlevel. The transistor 29 in the clip circuit 27 thereby turns on tosupply the clipping voltage VC to the non-inverting input terminal ofthe operational amplifier 20. The clipping voltage VC is configured sothat an output voltage from the operational amplifier 20 becomesslightly lower than the threshold VTH for the latch circuit 21.

The seventh modification provides the same effect as the firstembodiment. The seventh modification may also configure the clippingvoltage VC so that the voltage at the output terminal T3 of theoperational amplifier 20 becomes higher than the threshold voltage VTHfor the latch circuit 21 when the stop signal ST goes to the L level. Inthis case, the transient current IT4 may flow through the bias voltagesupply lines VPL and VNL if the clipping voltage VC is applied to theoutput terminal T3 of the operational amplifier 20. The transientcurrent IT4 has the polarity opposite the transient current IT3illustrated in FIG. 7F. The transient current IT4 may cancel thetransient current IT3.

Eighth Modification

FIG. 15 illustrates an AD converter 75 according to the eighthmodification. A clip circuit 76 and a latch circuit 79 replace the clipcircuit 27 and the latch circuit 21, respectively. The clip circuit 76includes switches 77 and 78. One terminal of the switch 77 receives thecontrol voltage VCA. The other terminal thereof is coupled to theinverting input terminal of the operational amplifier 20 via the switch78. The control voltage VCA is set to be lower than a lower limit of theramp voltage VR.

The control signal CNT controls the switch 77. The switch 77 turns offwhile the switch SW2 turns on. The switch 78 turns on while theinversion signal /ST for the stop signal ST is set to the H level. Theswitch 78 turns off while the inversion signal /ST is set to the Llevel. The latch circuit 79 is provided by adding an inverter 80 to thelatch circuit 21. The inverter 80 generates the inversion signal /ST forthe stop signal St occurring at the node N25 and supplies the inversionsignal /ST to the switch 78.

A signal output from the operational amplifier 20 transitions from the Hlevel to the L level. Turning on the transistor 22 in the latch circuit21 raises the inversion signal /ST for the stop signal ST to the H levelfrom the L level. The switch 78 in the clip circuit 76 thereby turns on.The control voltage VCA is supplied to the inverting input terminal ofthe operational amplifier 20. The output voltage for the operationalamplifier 20 is raised to the H level (power supply voltage VDD).

The eighth modification forces the amplitude of an output signal fromthe operational amplifier 20 to be smaller than the comparative exampleand decreases a transient current flowing through the bias voltagesupply lines VPL and VNL. The transient current IT4 may flow through thebias voltage supply lines VPL and VNL when a signal output from theoperational amplifier 20 goes to the H level. The transient current IT4has the polarity opposite the transient current IT3 illustrated in FIG.7F. The transient current IT4 may cancel the transient current IT3.

Ninth Modification

FIG. 16 illustrates an AD converter 81 according to the ninthmodification. The N-channel MOS transistor 47 configures the switch SW2.An AND gate 82, an OR gate 83, and a switch 84 replace the clip circuit27. A latch circuit 79 replaces the latch circuit 21. The drain of thetransistor (switch SW2) is coupled to the output terminal of theoperational amplifier 20. The source thereof is coupled to the invertinginput terminal of the operational amplifier 20.

The AND gate 82 outputs an AND signal between a control circuit CNT1 andoutput signal /ST from the latch circuit 79. The OR gate generates anAND signal between a control circuit CNT2 and an output signal from theAND gate 82 and supplies the AND signal to the gate of the transistor47. One switch terminal 84 a of the switch 84 is coupled to the otherelectrode of the capacitor C2. The other switch terminal 84 b thereofreceives the control voltage VCA. A common terminal 84 c thereof iscoupled to the non-inverting input terminal of the operational amplifier20. The switch 84 turns on between the terminals 84 a and 84 c when asignal output from the AND gate is set to the L level. The switch 84turns on between the terminals 84 b and 84 c when a signal output fromthe AND gate is set to the H level.

A control signal CNT2 controls the transistor 47 (switch SW2). Thecontrol signal CNT2 is set to the H level to turn on the transistor 47when the capacitor C1 maintains the reference voltage VIB for the analogsignal. Otherwise, the control signal CNT2 is set to the L level.

A control signal CNT1 controls the transistor 47 (SW2) and the switch84. The control signal CNT1 is set to the H level when the voltage VIPmaintained in the capacitor C2 is converted into the digital signal DO.Otherwise, the control signal CNT1 is set to the L level.

Setting the reset signal RST to the H level for a specified time resetsthe latch circuit 79 and sets the signal /ST to the L level. A signaloutput from the AND gate 82 thereby goes to the L level. The switch 84turns on between the terminals 84 a and 84 c. The other electrode of thecapacitor C2 is coupled to the non-inverting input terminal of theoperational amplifier 20.

The capacitors C1 and C2 are charged to the reference voltage VIB andthe signal voltage VIP, respectively. After that, the ramp voltage VRgradually decreases from the highest value to the lowest value. Anoutput voltage of the operational amplifier 20 gradually transitionsfrom the H level to the L level. When the output voltage of theoperational amplifier 20 becomes lower than the threshold voltage VTHfor the latch circuit 79, the transistor 22 turns on to raise the signal/ST to the H level from the L level. A signal output from the AND gate82 thereby goes to the H level. A signal output from the OR gate 83 alsogoes to the H level. As a result, the transistor 47 turns on. The switch84 turns on between the terminals 84 b and 84 c. The output voltage ofthe operational amplifier 20 is used as the control voltage VCA. In thiscase, the control voltage VCA is configured so that the output voltageof the operational amplifier 20 is slightly lower than the thresholdvoltage VTH for the latch circuit 79, for example.

The ninth modification also provides the same effect as the firstembodiment. The ninth modification may configure the control voltage VCAso that the output voltage of the operational amplifier 20 becomeshigher than the threshold voltage VTH for the latch circuit 79 when thesignal /ST goes to the H level. In this case, the transient current IT4may flow through the bias voltage supply lines VPL and VNL when theoutput voltage of the operational amplifier 20 becomes the controlvoltage VCA. The transient current IT4 has the polarity opposite thetransient current IT3 illustrated in FIG. 7F. The transient current IT4may cancel the transient current IT3.

Tenth Modification

FIG. 17 illustrates an AD converter 85 according to the tenthmodification. A capacitor 86, a NAND gate 87, and a switch 88 replacethe clip circuit 27. A latch circuit 79 configures the latch circuit 21.The capacitors C2 and 86 are coupled in series between the non-invertinginput terminal of the operational amplifier 20 and the line for theground voltage VSS. The NAND gate 87 outputs an inversion signal for theAND signal between the signal /ST output from the latch circuit 79 andthe control signal CNT3. One terminal of the switch 88 receives the rampvoltage VR. The other terminal thereof is coupled to a node between thecapacitors C2 and 86. The switch 88 turns on when a signal output fromthe NAND gate 87 is H level. The switch 88 turns off when a signaloutput from the NAND gate 87 is L level.

The control signal CNT3 controls the switch 88. The control signal CNT3is set to the H level when the voltage VIP maintained in the capacitorC2 is converted into the digital signal DO. Otherwise, the controlsignal CNT3 is set to the L level. When the control signal CNT3 is setto the L level, a signal output from the NAND gate is set to the Hlevel. The switch 88 turns on to supply the ramp voltage VR to the nodebetween the capacitors C2 and 86.

Setting the reset signal RST to the H level for a specified time resetsthe latch circuit 79 and sets the signal /ST to the L level. Thecapacitors C1 and C2 are charged to the reference voltage VIB and thesignal voltage VIP, respectively. After that, the control signal CNT3 isset to the H level.

The ramp voltage VR gradually decreases from the highest value to thelowest value. An output voltage of the operational amplifier 20gradually transitions from the H level to the L level. When the outputvoltage of the operational amplifier 20 becomes lower than the thresholdvoltage VTH for the latch circuit 79, the transistor 22 turns on toraise the signal /ST to the H level from the L level. A signal outputfrom the NAND gate 87 thereby goes to the L level. The switch 88 turnsoff to keep constant a voltage for the node between the capacitors C2and 86 and stop the output voltage of the operational amplifier 20 fromtransitioning. The tenth modification also provides the same effect asthe first embodiment.

Second Embodiment

FIG. 18 is a block diagram illustrating a configuration of a solid-stateimaging apparatus 90 according to the second embodiment of theinvention. As illustrated in FIG. 18, the solid-state imaging apparatus90 includes a pixel array 91, AD converters 92 and 93, and a controlcircuit 94. The pixel array 91 has the same configuration as that of thepixel array 1 illustrated in FIG. 1. The pixel array 91 includes pixelcircuits 2, row selection line groups (not illustrated), and signallines 4. The pixel circuits 2 are provided for columns and rows. The rowselection line groups are provided corresponding to the rows. The signallines 4 are provided corresponding to the columns.

A series of AD converters 92 is provided along one side (top side inFIG. 18) of the pixel array 91. The AD converters 92 correspond toodd-numbered columns of the pixel array 91. Each AD converter 92 iscoupled to the signal line 4 for the corresponding column.

A series of AD converters 93 is provided along the other side (bottomside in FIG. 18) of the pixel array 91. The AD converters 93 correspondto even-numbered columns of the pixel array 91. Each AD converter 93 iscoupled to the signal line 4 for the corresponding column.

The control circuit 94 includes the vertical scanning circuit 5, thecontrol circuit 6, and the horizontal scanning circuit 7 illustrated inFIG. 1. The control circuit 94 successively selects the rows at aspecified time interval and allows the row selection line group for theselected row to activate the pixel circuit 2 corresponding to the row.The pixel circuit 2 includes a photo diode and a selection transistor.The pixel circuit 2 for the selected row outputs the reference voltageVIB for the analog signal to the corresponding signal line 4 during thefirst period and outputs the signal voltage VIP for the analog signal tothe corresponding signal line 4 during the second period.

While one row is selected, the control circuit 94 successively selectsthe signal lines 4 at a specified time interval. The AD converters 92and 93 are supplied with an analog signal from the activated pixelcircuit 2 via the corresponding signal line 4 and convert the analogsignal into the digital signal DO based on the ramp voltage VR from thecontrol circuit 94. The AD converters 92 and 93 output the generateddigital signal DO to the outside via the data bus when the controlcircuit 94 selects the corresponding signal line 4.

FIG. 19 is a block diagram illustrating a configuration of the ADconverter 92 for comparison with FIG. 3. The AD converter 92 differsfrom the AD converter 8 in FIG. 3 in that a clip circuit 96 replaces theclip circuit 27 and control signal CNT4 replaces the control signal CNT.A logical-level voltage for the control signal CNT4 is set to aspecified bias value (to be described) instead of a digital valuespecified in the power supply voltage VDD or the ground voltage VSS. Theclip circuit 96 is provided by removing the transistors 28 and 29 fromthe clip circuit 27. The drain of the transistor 30 receives the powersupply voltage VDD. The source thereof is coupled to the output terminalof the operational amplifier 20. The gate thereof receives the controlsignal CNT4.

The control signal CNT4 is set to the L level while the switch SW2 turnson. Otherwise, the control signal CNT4 is set to the H level. A voltagevalue for the control signal CNT4 at the L level is configured so thatthe source potential of the transistor 30 is lower than the referencevoltage VIP of the analog signal. This is because the reference voltageVIB for the analog signal needs to be applied to the inverting inputterminal of the operational amplifier 20 while the switch SW2 turns on.

If the source potential of the transistor 30 is higher than thereference voltage VIB, the source potential of the transistor 30 isapplied to the inverting input terminal. The reference voltage VIBcannot be correctly applied to the inverting input terminal. To solvethis problem, the control signal CNT4 needs to be lowered to the voltagevalue for the L level so that the clip circuit 96 does not operateduring this period. For example, suppose the reference voltage VIB is1.2 V and the threshold voltage for the transistor 30 is 0.7 V. Then,the gate potential of the transistor 30 just needs to be lower than1.2+0.7=1.9 V. Accordingly, the L level for the control signal CNT4 isset to 1.5 V, for example.

When the control signal CNT4 is set to the H level, the transistor 30operates as a source follower. The clipping voltage VC is supplied tothe output terminal of the operational amplifier 20. The clippingvoltage VC, i.e., the source potential of the transistor 30, is lowerthan the gate potential by the threshold voltage for the transistor 30.The clipping voltage VC is configured to be slightly lower than thethreshold voltage VTH for the latch circuit 21. The AD converter 93 hasthe same configuration as the AD converter 92.

FIG. 20 is a circuit block diagram illustrating a configuration of aseries of AD converters 93. As illustrated in FIG. 20, one signal φ1controls the switches SW1 in the AD converters 93. One signal φ2controls the switches SW2. One control signal CNT4 controls thetransistors 30. As illustrated in FIG. 2, the operational amplifiers 20are provided with the bias voltage supply lines VPL and VNL in common.

FIG. 21 is a timing chart illustrating output voltage VO of theoperational amplifier 20. At time t0 in FIG. 21, the output voltage VOof the operational amplifier 20 starts transitioning from the H level VHto the L level VL. The output voltage VO of the operational amplifier 20does not drop at a constant speed. Suppose drop speed vb during periodTb under the condition of VO<VK and drop speed va during period Ta underthe condition of VO>VK. Then, drop speed vb is higher than drop speedva. A change in the voltage VO causes a noise to occur on the biasvoltage supply lines VPL and VNL if the AD converter 40 according to thecomparative example illustrated in FIG. 6 is used. The noise occursmainly during period Tb. Therefore, the clipping voltage VC is favorablyspecified between the threshold voltage VTH and voltage VK.

FIG. 22 is a timing chart illustrating operations of the AD converter 92illustrated in FIG. 19. If the vertical scanning circuit 5 selects arow, the pixel circuits 2 corresponding to the row are activated. At t0,the pixel circuits 2 are reset and output the reference voltage VIE(black level) for an analog signal to the signal line 4.

At time t1, the control signal CNT4 lowers from the H level (e.g., 2.5V) to the L level (e.g., 1.5 V) to turn off the transistor 30. At timet2, the switches SW1 and SW2 turn on to charge the inverting inputterminal T2 of the operational amplifier 20 with the reference voltageVIB for the analog signal.

At time t3, the switches SW1 and SW2 turn off and the control signalCNT4 is set to the H level. The transistor 30 thereby operates as asource follower. The output terminal of the operational amplifier 20 ischarged with the clipping voltage VC. At time t4, each pixel circuit 2corresponding to the selected row outputs the signal voltage VIP for theanalog signal to the signal line 4. Between time t4 and t5, the rampvoltage VR linearly drops from the highest value VRH to high value VRhin proportion to the time lapse. An offset voltage for the operationalamplifier 20 is measured during this period. Since the offset voltage issmall, a small voltage difference is provided between the highest valueVRH and the high value VRh for the ramp voltage VR.

While the ramp voltage VR drops in proportion to the time, thecapacitive coupling via the capacitor C2 also drops the voltage at thenon-inverting input terminal in proportion to the time. The voltage atthe non-inverting input terminal becomes lower than the voltage at theinverting input terminal. The operational amplifier 20 then allows thevoltage at the output terminal to transition to the L level VL from theH level VH.

The voltage at the output terminal of the operational amplifier 20reaches the threshold voltage VTH for the latch circuit 21. Then, thetransistor 22 turns on to lower the stop signal ST from the H level tothe L level. The counter latch 26 thereby latches the signal CT outputfrom the counter 11. The latched signal CT becomes the digital signalDO. At this time, the digital signal DO1 indicates the offset voltage ofthe operational amplifier 20.

Between time t6 and t7, the switch SW1 turns on. The non-inverting inputterminal of the operational amplifier 20 is thereby charged with thesignal voltage VIP for the analog signal. The output terminal of theoperational amplifier 20 is set to the H level VH. Between time t8 andt9, the ramp voltage VR linearly drops from the highest value VRH to thelowest value VRL in proportion to the time lapse. The signal voltage VIPof the analog signal is measured during this period. The signal voltageVIP rises in proportion to the amount of incident light on the pixelcircuit 2. A large voltage difference is provided between the highestvalue VRH and the lowest value VRL for the ramp voltage VR.

While the ramp voltage VR drops in proportion to the time, thecapacitive coupling via the capacitor C2 also drops the voltage at thenon-inverting input terminal in proportion to the time. The voltage atthe non-inverting input terminal becomes lower than the voltage at theinverting input terminal. The operational amplifier 20 then allows thevoltage at the output terminal to transition to the L level VL from theH level VH.

The voltage at the output terminal T3 of the operational amplifier 20reaches a voltage that is lower than the threshold voltage VTH for thelatch circuit 21. Then, the transistor 22 turns on to lower the stopsignal ST from the H level to the L level. The counter latch 26 therebylatches the signal CT output from the counter 11. The latched signal CTbecomes the digital signal DO. At this time, the digital signal DO2indicates a voltage difference between the signal voltage VIP and thereference voltage VIB for the analog signal. A difference between thedigital signals DO2 and DO1 indicates the amount of incident light onthe pixel circuit 2. The second embodiment provides the same effect asthe first embodiment.

The above-mentioned solid-state imaging apparatus is formed on asemiconductor chip and is applied to a camera system. The pixel arrayreceives the incident light through a lens in the camera system. Adigital signal generated from the solid-state imaging apparatus isoutput to a signal processing portion of the camera system via the databus.

The above-mentioned embodiments should be regarded as illustrativeexamples, not regarded as being restrictive, in all aspects. Theappended claims, not the above description, provide the scope of theinvention. This intends to include all changes in meanings and rangesequivalent to the appended claims.

What is claimed is:
 1. A solid-state imaging apparatus comprising: aplurality of pixel circuits, each of which outputs an analog signalresponding to an amount of incident light; a plurality of row selectionlines and a plurality of signal lines coupled to the plurality of pixelcircuits; a plurality of AD converters, each of which is coupled to oneof the signal lines and is configured to convert an analog signal froman activated pixel circuit in the plurality of pixel circuits into adigital signal, each of the AD converters comprising: an operationalamplifier having an input node for inputting the analog signal from theactivated pixel circuit via the signal line, and an output node; and abias voltage supply line configured to supply a bias voltage to each ofthe plurality of AD converters, wherein a power supply voltage issupplied to the operational amplifier in each of the AD converters,wherein a clip circuit is coupled to the output node of the operationalamplifier, which is configured to make an amplitude of a voltage levelof the output node of the operational amplifier less than the powersupply voltage.
 2. A solid-state imaging apparatus according to claim 1,wherein the clip circuit is comprised of an N-type MOSFET, wherein thepower supply voltage is supplied to a drain electrode of the N-typeMOSFET, wherein a source electrode of the N-type MOSFET is coupled tothe output node of the operational amplifier.
 3. A solid-state imagingapparatus according to claim 1, wherein the plurality of pixel circuitsare disposed in rows and columns.
 4. A solid-state imaging apparatusaccording to claim 1, wherein a control circuit configured to select oneof the row selection lines and activate each pixel circuit is disposed.5. A solid-state imaging apparatus according to claim 1, wherein thebias voltage is supplied to the operational amplifier.
 6. A solid-stateimaging apparatus according to claim 4, wherein the operationalamplifier is comprised of a plurality of MOSFETs, wherein the biasvoltage is supplied to agate electrode of a MOSFET in the plurality ofMOSFETs.
 7. A solid-state imaging apparatus according to claim 1,wherein the operational amplifier includes a current mirror circuit. 8.A solid-state imaging apparatus according to claim 1, wherein a latchcircuit is coupled to the output node of the operational amplifier.